1. Field of the Invention
The invention is relates to a floating gate, and more particularly to a floating gate with multiple tips and a method for fabricating the same.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
An advantage of EPROM is that it is electrically programmed, but for erasing, still requires exposure to ultraviolet (UV) light.
In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory.
FIGS. 1a to 1c are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory.
In FIG. 1a, a silicon substrate 101 is provided. A gate oxide layer 102, a doped polysilicon layer 103, and a nitride layer 104 having an opening 105 are sequentially formed on the silicon substrate 101.
In FIG. 1b, the doped polysilicon layer 105 exposed by the opening 105 is oxidized to form an oxide layer 106 with a Bird""s Beak shape edge.
In FIG. 1c, the nitride layer 104 is removed. The doped polysilicon layer 103 is anisotropically etched to form a floating gate 103a using the oxide layer 106 as an etching mask.
A split gate flash memory is completed after a control gate is formed on the floating gate and the silicon substrate 101 is implanted to form source/drain devices.
In the program step, high voltage is applied between the source and drain. More high voltage is applied to the control gate and goes to the floating gate by the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The voltage is injected into the floating gate through the film gate oxide layer from the drain.
In the erase step, high voltage is applied between the drain and the control gate. A high electric field is produced on the film gate oxide layer by the electric capacity coupling. The voltage is injected into the drain through the film gate oxide layer from the floating gate. The gate oxide layer is damaged by the high voltage.
When the edge of the floating gate is a tip, the electrical field is easily concentrated, and the point is easily discharged. If the point discharge is increased, erasing effect is stronger.
In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices.
The present invention is directed to a floating gate with multiple tips and a method for fabricating the same.
Accordingly, the present invention provides a method for forming a floating gate. A semiconductor substrate is provided. A gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed on the surface of the semiconductor substrate. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the patterned hard mask layer as a mask. The patterned hard mask layer is removed.
Accordingly, the present invention also provides a method for forming a floating gate. A semiconductor substrate is provided. A gate dielectric layer, a conducting layer, a hard mask layer, and a patterned resist layer are sequentially formed on the surface of the semiconductor substrate. The surface of the hard mask layer is covered by the patterned resist layer to form a gate. The patterned resist layer is removed. The conducting layer is etched to form a remaining conducting layer using the hard mask layer as a mask. The remaining conducting layer is oxidized to form an oxide layer on the surface of the exposed conducting layer and the exposed remaining conducting layer. The oxide layer and the conducting layer are sequentially etched to form a multiple tip conducting layer as a floating gate using the hard mask layer as a mask. The hard mask layer and the exposed oxide layer are removed.
Accordingly, the present invention also provides a floating gate formed on the surface of the semiconductor substrate comprising a conductive base and a conductive protruding layer. The conductive base has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the semiconductor substrate. The conductive protruding layer protrudes from the conductive base. The conductive protruding layer has a flat top. The conductive protruding layer has a second top portion and a second bottom portion. An edge of the top portion is a second tip. The second bottom portion contacts the first top portion. The conductive protruding layer has two concave sidewalls. A multiple tip floating gate is composed of the conductive base and the conductive protruding layer.
Accordingly, the present invention also provides a floating gate formed on the semiconductor substrate, and a gate dielectric layer is formed between the floating gate and the semiconductor substrate. The floating gate comprises a base poly layer and a protruding poly layer. The base poly layer has a first top portion and a first bottom portion. An edge of the first top portion is a first tip. The first bottom portion contacts the gate dielectric layer. The protruding poly layer protrudes from the base poly layer. The protruding poly layer is flat top. The protruding poly layer has a second top portion and a second bottom portion. An edge of the second portion is a second tip. The second bottom portion contacts the first top portion. The protruding poly layer has two concave sidewalls. A multiple tip floating gate is composed of the base poly layer and the protruding poly layer.